Renesas Electronics S5D3 Synergy™ Platform Microcontrollers
Renesas Electronics S5D3 Synergy™ Platform Microcontrollers incorporates a high-performance Arm Cortex®-M4 core running up to 120MHz. The S5D3 MCUs integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of peripherals, facilitating design scalability and efficient platform-based product development. The S5D3 Synergy™ Platform Microcontrollers feature 512KB Code flash, 8KB data flash, and 256KB SRAM. Additional features include capacitive touch sensing unit, USB 2.0 full-speed, SDHI, quad SPI, security and safety features, and advanced analog.
Features
Arm Cortex-M4 Core with Floating Point Unit (FPU)
Armv7E-M architecture with DSP instruction setMaximum operating frequency: 120MHzSupport for 4GB address spaceOn-chip debugging system: JTAG, SWD, and ETMBoundary scan and Arm Memory Protection Unit (Arm MPU)Memory
512KB code flash memory (40MHz zero wait states)8KB data flash memory (125,000 erase/write cycles)256KB SRAMFlash Cache (FCACHE)Memory Protection Units (MPU)Memory Mirror Function (MMF)128-bit unique IDConnectivity
USB 2.0 Full-Speed (USBFS) moduleOn-chip transceiverSerial Communications Interface (SCI) with FIFO × 7Serial Peripheral Interface (SPI) × 2I2C bus interface (IIC) × 2CAN module (CAN) × 2Serial Sound Interface Enhanced (SSIE)SD/MMC Host Interface (SDHI) × 2Quad Serial Peripheral Interface (QSPI)IrDA interfaceSampling Rate Converter (SRC)External address space8-bit bus spaceAnalog
12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits each × 212-bit D/A Converter (DAC12) × 2High-Speed Analog Comparator (ACMPHS) × 6Programmable Gain Amplifier (PGA) × 6Temperature Sensor (TSN)Safety
Error Code Correction (ECC) in SRAMSRAM parity error checkFlash area protectionADC self-diagnosis functionClock Frequency Accuracy Measurement Circuit (CAC)Cyclic Redundancy Check (CRC) calculatorData Operation Circuit (DOC)Port Output Enable for GPT (POEG)Independent Watchdog Timer (IWDT)GPIO readback level detectionRegister write protectionMain oscillator stop detectionIllegal memory access
Armv7E-M architecture with DSP instruction setMaximum operating frequency: 120MHzSupport for 4GB address spaceOn-chip debugging system: JTAG, SWD, and ETMBoundary scan and Arm Memory Protection Unit (Arm MPU)Memory
512KB code flash memory (40MHz zero wait states)8KB data flash memory (125,000 erase/write cycles)256KB SRAMFlash Cache (FCACHE)Memory Protection Units (MPU)Memory Mirror Function (MMF)128-bit unique IDConnectivity
USB 2.0 Full-Speed (USBFS) moduleOn-chip transceiverSerial Communications Interface (SCI) with FIFO × 7Serial Peripheral Interface (SPI) × 2I2C bus interface (IIC) × 2CAN module (CAN) × 2Serial Sound Interface Enhanced (SSIE)SD/MMC Host Interface (SDHI) × 2Quad Serial Peripheral Interface (QSPI)IrDA interfaceSampling Rate Converter (SRC)External address space8-bit bus spaceAnalog
12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits each × 212-bit D/A Converter (DAC12) × 2High-Speed Analog Comparator (ACMPHS) × 6Programmable Gain Amplifier (PGA) × 6Temperature Sensor (TSN)Safety
Error Code Correction (ECC) in SRAMSRAM parity error checkFlash area protectionADC self-diagnosis functionClock Frequency Accuracy Measurement Circuit (CAC)Cyclic Redundancy Check (CRC) calculatorData Operation Circuit (DOC)Port Output Enable for GPT (POEG)Independent Watchdog Timer (IWDT)GPIO readback level detectionRegister write protectionMain oscillator stop detectionIllegal memory access
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